Parallel Data Architectures & Brain Computer Interface Group.
Efficient System and Devices
Architectural optimization has traditionally been a heuristic process involving multiple iterations before the design converges to the desired specifications. Multiple architectures are difficult to evaluate if RTL is written repeatedly for each design. The process becomes tedious if the design fails to meet target specifications and changes need to be made at the system level. This work aims to automate the process of architecture selection and provide energy-area-performance optimal solutions staring from the graphical timed data-flow Matlab/Simulink description of the algorithm.
Spike sorting is the process of determining which action potential originated from which neuron during extracellular recordings. Applications such as brain-machine interfaces (BMIs) require hardware spike sorting in order to 1) obtain single-unit activity and 2) perform data reduction for wireless transmission of data under limited-bandwidth conditions. Such systems must be low-power, low-area, high-accuracy, unsupervised, and able to operate in real time. Several detection, feature-extraction, and clustering algorithms for spike sorting are currently being evaluated in terms of accuracy versus computational complexity. The best algorithms will be implemented in hardware.
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